The development of the semiconductor integrated circuit is very rapid since it appears as a new generation electronic device. In recent twenty years, the semiconductor integrated circuit undergoes three development phases, from small scale, middle scale to large scale. At present, the semiconductor integrated circuit is developing toward to the very-large-scale integration (VLSI) phase, and the development and application thereof have become one of the most active and important fields in modern science and technology.
The semiconductor integrated circuit chip undergoes a plurality of complicated processes to stack layers of polycrystalline silicon, silicon oxide, and metal interconnection one by one; so as to connect countless devices together to achieve complicated functions. In the process of semiconductor integrated circuit chip designing and manufacturing, failure analysis and the like is very important. The chip designer can perform a targeted test for chip problems by the failure analyses so as to quickly and accurately verify the design scheme, and if there is a problem in a region of the chip, the region will be isolated so as to find the reason of the problem. It is needed to prepare a plan-view TEM sample before the failure analyses are performed.
The TEM is one of the most important instruments in research of material, and it is also be used in the fundamental research, development and application of the Nanotechnology. The characteristic of this technology is to directly cut out a film, which may be researched by TEM or high resolution electron microscopy, from a specimen in nanometer or micrometer dimensions. Another characteristic of this technology is not to damage the original structure of the specimen.
The TEM has been widely applied in various fields including the integrated circuit analysis and the application thereof becomes more and more important, while the sample prepared by Focused Ion Beam (FIB) is a major means of TEM sample preparation in the semiconductor field. In addition to cross-sectional TEM samples, it is mostly necessary to make a planar TEM analysis. At present, the preparation of the plan-view TEM sample is mainly completed by using FIB.
The FIB is to generate a secondary electron signal by irradiating the surface of the sample with an ion beam which is generated from a liquid metal (Ga) ion source, accelerated and focused by an ion gun, thus obtain an electron image. Such function is similar to that of SEM (Scanning electron microscope), or to complete the surface topography processing in micrometer or nanometer scale by stripping the surface atom with a strong current ion beam. Generally, metal, silicon oxide layer or metal deposition layer is selectively stripped by a physical sputtering method with a chemical gas reaction.
The flow of the plan-view TEM sample preparation in prior art is mainly as follows:
Firstly, lying a sample of the semiconductor integrated circuit chip on a platform, and making the cross section of the sample close to a target region by cleaving or polishing (as shown in FIG. 1);
Then, cutting a first plane (as shown in FIG. 2) and a second plane (as shown in FIG. 3) of the sample with FIB;
Finally, forming the TEM sample (as shown in FIG. 4).
It is clear for persons skilled in the art that, in reverse engineering analysis, for example, when the reverse engineering analysis is performed on a certain chip, it is needed to prepare a plan-view TEM sample in a certain region on the chip to analyze the structure such as polycrystalline silicon gate (Poly Gate), while the rest chip needs to be kept well so as to enable more region analysis later. However, the first step of the above process of preparing the plan-view TEM sample needs to cleave or polish the sample to an extent that the cross section of the sample is close to the target region, and this step will cause a large amount of region on the chip be completely removed, which will cause subsequence analyses difficult to perform or could not perform at all.
Therefore, how to obtain the planar TEM data in the target region while the rest of chip is not damaged, is a new challenge for people in this field.